1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns a device and a fabrication process, whereby a magnetic memory structure may be formed.
2. Description of the Related Art
Magnetic memory is a developing technology that offers the advantages of non-volatile memory with high-density fabrication. Magnetic memory structures, such as magneto-resistive random access memory (MRAM), manipulate the magnetic properties of layered magneto-resistive materials to produce a selective resistance differential across the magnetic memory structure. In one aspect, magnetic memory structures utilize selective resistance by controlling the alignments of spin states within multiple layers of material to increase or decrease the resistance of a material. Selectively altering the spin states of magneto-resistive materials results in selectively altering the resistance of the magnetic memory structure, which may be sensed thereby permitting the use of layered magneto-resistive materials in logic state devices.
Conventional magnetic memory devices may comprise a stacked structure that may include a hard (high coercivity) layer, a soft (low coercivity) layer, and a non-magnetic layer interposed therebetween. The soft or sense layer may be programmed through the application of proximate magnetic field and the net magnetization vectors between the programmable layer and the hard layer may be changed between two discrete quantities, which may then be sensed to detect the programmed logic state of the magnetic memory device.
Additionally, magnetic memory devices, including MRAM, may also be referred to as a magnetic memory bit. Magnetic memory bits may utilize various technologies associated with at least one of, but is not limited to an anisotropic magnetoresistance (AMR) bit, a giant magnetoresistance (GMR) bit, a pseudo-spin valve (PSV) bit, and a spin-dependent tunneling (SDT) bit. A plurality of magnetic memory bits and the conductors that influence and/or access the magnetic memory bits may be arranged in a grid array, which may be formed on a semiconductor substrate layer, such as silicon. In a grid array, magnetic memory bits may be positioned adjacent one another and arranged on the substrate so as to be co-planar.
Due to the co-planar arrangement of conventional magnetic memory bits in a magnetic memory grid array, the areal density of the magnetic memory bits within the substrate plane is bounded by at least the amount of planar space available on the upper surface of the substrate. Other factors that may contribute to limiting density of conventional magnetic memory bits include physical size of the magnetic memory bits and the level at which fringe magnetic fields affect neighboring magnetic memory bits. Therefore, there exists a need to increase the fabrication density of magnetic memory bits, devices and/or structures without adversely affecting the performance, reliability, and functionality of the magnetic memory bits, devices, and/or structures.